The present invention relates generally to integrated circuit (IC) designs, and more particularly to an electrostatic discharge (ESD) protection system for multi-power domain circuitry.
A gate dielectric of a metal-oxide-semiconductor (MOS) transistor of an IC is very susceptible to damage. The gate dielectric may be destroyed by being contacted with a voltage only a few volts higher than a supply voltage of the IC. It is understood that a regular supply voltage is typically 5.0, 3.3 volts or even lower. Electrostatic voltages from common environmental sources can easily reach thousands, or even tens of thousands of volts. Such voltages are destructive even though the charge and any resulting current are extremely small. For this reason, it is of critical importance to discharge any static electric charge as it builds up, before it damages the IC.
An ESD protection circuit is typically added to an IC at its bond pads, which are the connections for the IC to outside circuitry. For example, in an operating IC, electric power is supplied to a VDD pad, electric ground is supplied to a VSS pad, electronic signals are supplied from outside to some pads, and electronic signals generated by the core circuitry of the IC are supplied to other pads for delivery to external circuits and devices. During the normal operation, the ESD protection circuit blocks a current to flow therethrough and is effectively isolated from the normally operating core circuitry. During an ESD event, the ESD protection circuit is designed to switch on quickly, thereby dissipating the ESD current to ground before its damages any logic components of the IC.
As the semiconductor processing technology advances, the gate dielectric of MOS transistor becomes thinner and increasingly susceptible to the ESD current. This issue becomes more serious when the MOS transistor is used in a multi-power domain circuitry where a diode module is typically connected to an I/O ground bus between two power domains. When the ESD occurs, the diode module may induce the ESD current to flow through a damaging path other than the I/O ground bus as a desired path, thereby damaging the thin-gate-dielectric MOS transistors.
Therefore, it is desirable to design an ESD protection system for multi-power domain circuitry that allows the ESD current to dissipate through a predefined path.